lexs@nyapad ~/tmp/hdl $ cat counter.v module counter(input clk, input reset, output reg [3:0] q); always @ (posedge reset) q <= 4'b0000; always @ (posedge clk) q <= q + 1'b1; endmodule module main; reg clk; reg reset; wire [3:0] q; counter cnt(clk, reset, q); initial begin $display("Hello!"); clk = 0; reset = 1; #1; reset = 0; end always begin clk <= !clk; #1; end always @ (clk) $display("clk=%b q=%b", clk, q); endmodule lexs@nyapad ~/tmp/hdl $ iverilog counter.v -o counter lexs@nyapad ~/tmp/hdl $ ./counter | head -n 10 Hello! clk=0 q=xxxx clk=1 q=0000 clk=0 q=0001 clk=1 q=0001 clk=0 q=0010 clk=1 q=0010 clk=0 q=0011 clk=1 q=0011 clk=0 q=0100 ДА У МЕНЯ ЖЕ ОЛОЛОГИКА!!111 чего бы такого написать? :3